Large amounts of data are typically stored in mass-storage devices such as hard disk drives (HDD). A consumer may desire a large capacity flash-memory system, perhaps as a replacement for a hard disk. A solid-state disk (SSD) made from flash-memory chips has no moving parts and is thus more reliable than a rotating disk.
Mass-storage devices are block-addressable rather than byte-addressable, since the smallest unit that can be read or written is a page that is several 512-byte sectors in size. Flash memory is replacing hard disks and optical disks as the preferred mass-storage medium.
NAND flash memory is a type of flash memory constructed from electrically-erasable programmable read-only memory (EEPROM) cells, which have floating gate transistors. These cells use quantum-mechanical tunnel injection for writing and tunnel release for erasing. NAND flash is non-volatile so it is ideal for portable devices storing data. NAND flash tends to be denser and less expensive than NOR flash memory.
However, NAND flash has limitations. In the flash memory cells, the data is stored in binary terms—as ones (1) and zeros (0). One limitation of NAND flash is that when storing data (writing to flash), the flash can only write from ones (1) to zeros (0). When writing from zeros (0) to ones (1), the flash needs to be erased a “block” at a time. Although the smallest unit for read or program can be a byte or a word, the smallest unit for erase is a block.
Single Level Cell (SLC) flash and Multi Level Cell (MLC) flash are two types of NAND flash. The erase block size of SLC flash may be 128K+4K bytes while the erase block size of MLC flash may be 256K+8K bytes. Another limitation is that NAND flash memory has a finite number of erase cycles between 10,000 to 1,000,000, after which the flash wear out and becomes unreliable.
Comparing MLC flash with SLC flash, MLC flash memory has advantages and disadvantages in consumer applications. In the cell technology, SLC flash stores a single bit of data per cell, whereas MLC flash stores two or more bits of data per cell. MLC flash can have twice or more the density of SLC flash with the same technology. But the performance, reliability and durability may decrease for MLC flash.
Some MLC flash-memory chips have significant restrictions on writing. Samsung's K9G8G08U0M is a typical restrictive-write MLC flash chip. It has 2K data bytes per page, plus 64 spare bytes that can be used for ECC or other management purposes. There are 128 pages per flash block in this chip. The pages must be written in page order, not in a random order. The whole block of 128 pages must be erased together.
Write data from the host may be buffered by a flash memory controller before being written to the flash memory. For example, all pages in a block could be buffered in the flash memory controller before the whole block is written to flash memory.
However, MLC chips often have a huge number of pages per block. There may be 256 pages per block, and each page can have 8 sectors of 512-Kbytes each, plus spare areas. A buffer large enough to hold an entire block would exceed 1 GigaByte. Such a large buffer is prohibitively expensive for low-cost flash devices.
Smaller page-size buffers are much less expensive to include on the flash controller chip. However, when pages from the host are not in a sequential order, data that was already written to flash may need to be copied to a new block so that pages may be written in sequential order. Better algorithms and systems to manage and map pages to flash memory can reduce the penalty of out-of-order page writes.
Since the size of flash memory may be quite large, mapping tables can also explode in size. It may become too expensive to keep maps of the entire flash memory in the controller chip. Better algorithms and systems to manage these maps of flash memory can reduce the penalty for the mapping tables.
What is desired is a flash memory system that stores only partial maps in the controller chip. A flash controller that only partially maps logical host pages to physical flash pages is desirable to reduce storage requirements on the flash controller chip. Command queuing and re-ordering of commands from the host is also desirable when using partial logical-to-physical mapping tables.